FIG. 1 shows the typical CMOS active pixel image sensor 100. The basic component of the image sensor 100 is the array of photosensitive pixels 130. The row decoder circuitry 105 selects an entire row of pixels 130 to be sampled by the correlated double sampling (CDS) circuitry 125. The analog-to-digital converter 115 scans across the column decoders and digitizes the signals stored in the CDS 125. The analog-to-digital converter 115 may be of the type which has one converter for each column (parallel) or one high-speed converter to digitize each column serially. The digitized data may be directly output from the image sensor 100 or there may be integrated image processing 120 for defect correction, color filter interpolation, image scaling, and other special effects. The timing generator 110 controls the row and column decoders to sample the entire pixel array or only a portion of the pixel array.
FIG. 2 shows one pixel of a CMOS image sensor 100. There is a photodiode 151 to collect photo-generated electrons. When the signal is read from the photodiode 151 the RG signal is pulsed to reset the floating diffusion node 155 to the VDD potential through the reset transistor 150. The row select signal RSEL is turned on to connect the output transistor 153 to the output signal line through the row select transistor 154. CDS circuit 125 samples the reset voltage level on the output signal line. Next, the transfer transistor 152 is pulsed on and off to transfer charge from the photodiode 151 to the floating diffusion 155. The new voltage level on the output signal line minus the reset voltage level is proportional to the amount of charge on the floating diffusion.
The magnitude of the floating diffusion voltage change is given by V=Q/C where Q is the amount of charge collected by the photodiode 151 and C is the capacitance of the floating diffusion node 155. If the capacitance C is too small and the charge Q is too large, then the voltage output will be too large for the CDS circuit 125. This problem commonly occurs when the pixel size is 2.7 μm or larger and the power supply voltage VDD is 3.3 V or less. The prior art solution to this problem has generally consisted of placing extra capacitance on the floating diffusion node 155.
In FIG. 3, U.S. Pat. No. 6,730,897 discloses increasing the floating diffusion node 160 capacitance by adding a capacitor 161 connected between the floating diffusion 160 and GND. In FIG. 4, U.S. Pat. No. 6,960,796 discloses increasing the floating diffusion node 162 capacitance by adding a capacitor 163 connected between the floating diffusion 162 and the power supply VDD. The prior art does increase the floating diffusion node capacitance enough to ensure the maximum output voltage is within the power supply limit at maximum photodiode charge capacity. However, the prior art solution is not optimum for low light level conditions. When there is a very small amount of charge in the photodiode, the larger floating diffusion capacitance lowers the voltage output making it harder to measure small signals. A need exists to have a small floating diffusion capacitance (for increased voltage output) when imaging in low light levels and a large floating diffusion capacitance (to lower voltage output below the power supply range) when imaging in high light levels. This is a form of gain control within the pixel.
FIG. 5 shows a pixel with an extra “dangling” transistor 165 connected to the floating diffusion node 166. This pixel is from U.S. Patent Application Publication 2006/0103749A1. Switching on the transistor 165 with the AUX signal line increases the capacitance of the floating diffusion 166. This method of changing the floating diffusion capacitance requires four transistor gates 165, 167, 168, and 169 to closely surround and directly electrically connected to the floating diffusion node 166. The presence of four transistor gates does not allow for the smallest possible floating diffusion node capacitance. When the transistor 165 is turned off, the gate still adds some additional capacitance compared to the case where only three transistors are adjacent to the floating diffusion.
U.S. Pat. No. 7,075,049 also shows pixels with the ability to change the floating diffusion node capacitance. It also has the requirement of four transistors adjacent to the floating diffusion node. Therefore, the pixel designs in U.S. Pat. No. 7,075,049 does not provide for the smallest possible floating diffusion capacitance.
The present invention discloses a pixel where the floating diffusion capacitance can be changed. Furthermore, the present invention will only require three transistor gates to be adjacent to the floating diffusion and not require additional signal lines be added to the pixel.